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Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO
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an1010.arc
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EEPROGIX.ASC
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1987-06-10
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10KB
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223 lines
*************************************************************
* EEPROGIX.ASC 19/3/87 Revision 1.0 *
* *
* Written by R.Soja, Motorola, East Kilbride *
* Motorola Copyright 1987. *
* *
* This program loads S records from the host to *
* either a 2864 external EEPROM on the 68HC11 external bus, *
* or to the 68HC11's internal EEPROM. It can also be used *
* verify memory contents against an S record file or just *
* load RAM located on the 68HC11's external bus. *
* Each byte loaded is echoed back to the host. *
* When programming a 2864, data polling is used to detect *
* completion of the programming cycle. *
* As the host software always waits for the echo before *
* downloading the next byte, host transmission is suspended *
* during the data polling period. *
* Because the serial communication rate (~1mS/byte) is *
* slower than the 2864 internal timer timeout rate (~300uS) *
* page write mode cannot be used. This means that data *
* polling is active on each byte written to the EEPROM, *
* after an initial delay of approx 500uS. *
* *
* When the internal EEPROM is programmed,instead of data *
* polling, each byte is verified after programming. *
* In this case, the 500uS delay is not required and is *
* bypassed. *
* If a failure occurs, the program effectively hangs up. It *
* is the responsibility of the host downloader program to *
* detect this condition and take remedial action. *
* The BASIC program EELOAD just displays a 'Communication *
* breakdown' message, and terminates the program. *
* *
* When used in the verify mode, apart from the normal echo *
* back of each character, all differences between memory *
* and S record data are also sent back to the host. *
* The host software must be capable of detecting this, and *
* perform the action required. *
* The BASIC loader program EELOAD simply displays the *
* returned erroneous byte adjacent to the expected byte, *
* separated by a colon. *
* *
* Before receiving the S records, a code byte is received *
* from the host. i.e.: *
* ASCII 'X' for external EEPROM *
* ASCII 'I' for internal EEPROM *
* ASCII 'V' for verify EEPROM *
* *
* This program is designed to be used with the BASIC EELOAD *
* program. *
* Data transfer is through the SCI, configured for 8 data *
* bits, 9600 baud. *
* *
* Constants
TDRE EQU $80
RDRF EQU $20
MDA EQU $20
SMOD EQU $40
mS10 EQU 10000/3 10mS delay with 8MHz xtal.
uS500 EQU 500/3 500uS delay.
*
* Registers
BAUD EQU $2B
SCCR1 EQU $2C
SCCR2 EQU $2D
SCSR EQU $2E
SCDR EQU $2F
PPROG EQU $3B
HPRIO EQU $3C
CONFIG EQU $103F
*
* Variables. Note: They overwrite initialisation code!!!!
ORG $0
EEOPT RMB 1
MASK RMB 1
TEMP RMB 1
LASTBYTE RMB 1
*
* Program
ORG $0
LDS #$FF
LDX #$1000 Offset for control registers.
CLR SCCR1,X Initialise SCI for 8 data bits, 9600 baud
LDD #$300C
STAA BAUD,X
STAB SCCR2,X
BSET HPRIO,X,#MDA Force Special Test mode first,
*=>> MAINTAIN SPECIAL TEST MODE TO ALLOW B96D CONFIG REGISTER PROGRAMMING <<==
* BCLR HPRIO,X,#SMOD and then expanded mode. (From Bootstrap mode)
ReadOpt STS <EEOPT Default to internal EEPROM: EEOPT=0; MASK=$FF;
BSR READC Then check control byte for external or internal
CMPB #'I' EEPROM selection.
BEQ LOAD
CMPB #'X' If external EEPROM requested
BNE OptVerf
INC EEOPT then change option to 1
LDAA #$80
STAA <MASK and select mask for data polling mode.
BRA LOAD
*
OptVerf CMPB #'V' If not verify then
BNE ReadOpt get next character else
DEC EEOPT make EEOPT flag negative.
*
LOAD EQU *
BSR READC
CMPB #'S Wait until S1 or S9 received,
BNE LOAD discarding checksum of previous S1 record.
BSR READC
CMPB #'1
BEQ LOAD1
CMPB #'9
BNE LOAD
BSR RDBYTE Complete reading S9 record before terminating
TBA
SUBA #2 # of bytes to read including checksum.
BSR GETADR Get execution address in Y
LOAD9 BSR RDBYTE Now discard remaining bytes,
DECA including checksum.
BNE LOAD9
CPY #0 If execution address =0 then
BEQ * hang up else
JMP ,Y jump to it!
*
LOAD1 EQU *
BSR RDBYTE Read byte count of S1 record into ACCB
TBA and store in ACCA
SUBA #3 Remove load address & checksum bytes from count
BSR GETADR Get load address into X register.
DEY Adjust it for first time thru' LOAD2 loop.
BRA LOAD1B
*
LOAD1A LDAB EEOPT Update CC register
BMI VERIFY If not verifying EEPROM then
BEQ DATAPOLL If programming external EEPROM
LDAB #uS500
WAIT1 DECB then wait 500uS max.
BNE WAIT1
DATAPOLL LDAB ,Y Now either wait for completion of programming
EORB <LASTBYTE cycle by testing MS bit of last data written to
ANDB <MASK memory or just verify internal programmed data.
BNE DATAPOLL
LOAD1E DECA When all bytes done,
BEQ LOAD get next S record (discarding checksum) else
LOAD1B BSR RDBYTE read next data byte into ACCB.
INY Advance to next load address
TST EEOPT
BMI LOAD1D If verifying, then don't program byte!
BEQ PROG If internal EEPROM option selected then program
STAB ,Y else just store byte at address.
LOAD1D STAB <LASTBYTE Save it for DATA POLLING operation.
BRA LOAD1A
*
VERIFY LDAB ,Y If programmed byte
CMPB <LASTBYTE is correct then
BEQ LOAD1E read next byte
BSR WRITEC else send bad byte back to host
BRA LOAD1E before reading next byte.
*
READC EQU * ACCA, X, Y regs unchanged by this routine.
BRCLR SCSR,X,#RDRF,*
LDAB SCDR,X Read next char
WRITEC BRCLR SCSR,X,#TDRE,*
STAB SCDR,X and echo it back to host.
RTS Return with char in ACCB.
*
RDBYTE BSR READC 1st read MS nibble
BSR HEXBIN Convert to binary
LSLB and move to upper nibble
LSLB
LSLB
LSLB
STAB <TEMP
BSR READC Get ASCII char in ACCB
BSR HEXBIN
ORAB <TEMP
RTS Return with byte in ACCB
*
GETADR EQU *
PSHA Save byte counter
BSR RDBYTE Read MS byte of address
TBA and put it in MS byte of ACCD
BSR RDBYTE Now read LS byte of address into LS byte of ACCD
XGDY Put load address in Y
PULA Restore byte counter
RTS and return.
*
HEXBIN EQU *
CMPB #'9 If ACCB>9 then assume its A-F
BLS HEXNUM
ADDB #9
HEXNUM ANDB #$F
RTS
*
PROG EQU *
PSHA Save ACCA.
LDAA #$16 Default to byte erase mode
CPY #CONFIG If byte's address is CONFIG then use
BNE PROGA
LDAA #$06 bulk erase, to allow for A1 & A8 as well as A2.
PROGA BSR PROGRAM Now erase byte, or entire memory + CONFIG.
LDAA #2
BSR PROGRAM Now program byte.
CPY #CONFIG If byte was CONFIG register then
BNE PROGX
LDAB ,Y load ACCB with old value,to prevent hangup later.
PROGX PULA Restore ACCA
BRA LOAD1D and return to main bit.
*
PROGRAM EQU *
STAA PPROG,X Enable internal addr/data latches.
STAB ,Y Write to required address
INC PPROG,X Enable internal programming voltage
PSHX
LDX #mS10 and wait 10mS
WAIT2 DEX
BNE WAIT2
PULX
DEC PPROG,X Disable internal programming voltage
CLR PPROG,X Release internal addr/data latches
RTS and return
*
END